Static information storage and retrieval – Addressing
Patent
1980-02-11
1982-10-12
Moffitt, James W.
Static information storage and retrieval
Addressing
G11C 800
Patent
active
043542581
ABSTRACT:
A subtractor circuit subtracts start address information supplied from address information to produce a logical address. An adder circuit adds the start address information to memory capacity information to form the start address of the succeeding memory board. When 0.ltoreq.output information from the subtraction circuit<memory capacity information, a memory board is selected. To obtain the selection signal, a comparing circuit is provided which compares the output information from the subtractor circuit with the memory capacity information.
REFERENCES:
patent: 3796996 (1974-03-01), Curley et al.
patent: 3872452 (1975-03-01), Stoops
IBM Technical Disclosure Bulletin-vol. 15, No. 12, May 1973, pp. 3587-3591.
Moffitt James W.
Tokyo Shibaura Denki Kabushiki Kaisha
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