Memory bit line segment isolation

Details Memory bit line segment isolation Memory bit line segment isolation

2006-05-09

2006-05-09

Mai, Son (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S189040, C365S230030

Reexamination Certificate

active

07042765

ABSTRACT:
A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1BL0, Seg2BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.

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