Memory-based parallel data output controller

Details Memory-based parallel data output controller Memory-based parallel data output controller

1983-06-09

1984-03-06

Thomas, James D.

Boots, shoes, and leggings

G06F 300

Patent

active

044357818

ABSTRACT:
A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) (10) which has at least as many address locations as there are channels. A word counter addresses the RAM (10) which provides as its outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM (20) which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block (30) which selectively fills a shift register (40,42) used to drive the parallel data output bus (32). A strobe pulse is also generated which enables a decoder (34) to select the appropriate peripheral device using the encoded device number. A microcomputer connected to an address bus (16) can be used to set the contents of the RAMs via multiplexers (14,24) during the initialization phase using the technique of memory mapping.

REFERENCES:
patent: 3742466 (1973-06-01), Hamm
patent: 4016549 (1977-04-01), Hutner

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