Pulse or digital communications – Spread spectrum – Direct sequence
Patent
1980-03-12
1981-11-03
Safourek, Benedict V.
Pulse or digital communications
Spread spectrum
Direct sequence
375114, 375116, 370100, H04J 306, H04J 600
Patent
active
042989876
ABSTRACT:
The memory-based frame synchronizer comprises a serial-to-parallel converter which converts a serial input data stream to a constantly changing parallel data output. This parallel data output is supplied to programmable sync word recognizers each consisting of a multiplexer (18, 20, 22) and a random access memory (RAM) (38, 40, 42). The multiplexer is connected to both the parallel data output and an address bus (24) which may be connected to a microprocessor or computer for purposes of programming the sync word recognizer. The RAM is used as an associative memory or decoder and is programmed with the pattern of binary 1's and 0's necessary to identify a specific sync word. The RAM produces an output when the address supplied by the multiplexer corresponds to the specific sync word. Additional RAMs (62, 76, 78) are used as counter decoders to define word bit length, frame word length, and paragraph frame length. These RAMs have their address lines connected to a bit counter (50) and a word counter (66) by respective multiplexers (52, 70) which also connect the RAM address lines to the address bus (56). Thus, the counter decoder RAMs are also programmable to define the parameters or word bit length, frame word length, and paragraph frame length. The outputs of the recognizer RAMs and the counter decoder RAMs are connected to mode control and decoding logic (96, 98). There are three processing modes: the search mode in which there is a lack of coincidence between the sync outputs of the recognizer and counter decoder RAMs; the check mode in which there has been at least one coincidence but less than in successive coincidences between the sync outputs of the recognizer and counter decoder RAMs; and the lock mode in which there have been in successive coincidences between the sync outputs of the recognizer and counter decoder RAMs. The programmable RAMs permit dynamic and real time changes in formats under software control.
REFERENCES:
patent: 3903371 (1975-09-01), Colton
patent: 3920921 (1975-11-01), Pitroda
patent: 4131763 (1978-12-01), Herschtal
patent: 4158107 (1979-06-01), Nicholas
Niswander James K.
Stattel Raymond J.
Chin Stephen
Manning John R.
Safourek Benedict V.
Sandler Ronald F.
The United States of America as represented by the Administrator
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