Static information storage and retrieval – Read only systems
Reexamination Certificate
2006-03-23
2009-08-04
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Read only systems
C365S129000, C365S230010, C365S238500
Reexamination Certificate
active
07570505
ABSTRACT:
A high performance logic circuit optimizes a digital logic function by dividing the function into smaller blocks. Thus, the logic circuit is divided into smaller blocks. The smaller blocks are implemented with read-only memory (ROM), in which outputs corresponding to input combination are pre-stored. Inputs to each of the smaller blocks are used as an address to access the ROM.
REFERENCES:
patent: 5245562 (1993-09-01), Dettmer
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5359548 (1994-10-01), Yoshizawa et al.
patent: 5481486 (1996-01-01), Cliff et al.
patent: 5544115 (1996-08-01), Ikeda
patent: 5570039 (1996-10-01), Oswald et al.
patent: RE35977 (1998-12-01), Cliff et al.
patent: 5926036 (1999-07-01), Cliff et al.
patent: 6349374 (2002-02-01), Jin
patent: 6359466 (2002-03-01), Sharpe-Geisler
patent: 2007/0129924 (2007-06-01), Verheyen et al.
Kaeriyame, Shunichi et al., NonVolatile Programmable Solid-Electrolyte Nanometer Switch, I.E.E.E. Journal of Solid-State Circuits, vol. 40, No. 1, Jan. 2005.
Abu-Khater, Issam et al., j) Circuit Techniques for CMOS Low-Power High-Performance Multipliers, I.E.E.E., Journal of Solid-State Circuits, vol. 31, No. 10, Oct. 1996.
Kim, Myung-Soon et al, k) Look-Up Table-Based Pulse Shaping Filter Design, I.E.E.E., Electronics Letters, vol. 36, No. 17, Aug. 17, 2000, 2 pages (1505-1506).
Fonseca, M. et al., Design of a Radix-2-Hybrid Array Multiplier Using Carry Save Adder, SBCCI, Proceedings of the 18th annual symposium on Integrated circuits and system design, Florianolpolis, Brazil, Session: Low power digital circuits design, 2005, ISBN:1-59593-174-0, pp. 172-177.
Rafiquzzaman, M. and Chandra, R., “Modern Computer Architecture,” published by West Publishing Co., 1988, pp. 94-100.
Fonseca, M. et al., Design of a Radix-2-Hybrid Array Multiplier Using Carry Save Adder, SBCCI, Proceedings of the 18th annual symposium on Integrated circuits and system design, Florianolpolis, Brazil, Session: Low power digital circuits design, 2005, ISBN:1-59593-174-0, pp. 172-177, Sep. 4, 2005.
Orginos, I. et al., A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynomial Applications, I.E.E.E., in Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS'95), vol. 3, pp. 1992-1995, Seattle, 1995.
XILINK Adder/Subtractor v7.0 Product Specification, DS214 Apr. 28, 2005, pp. 1-6.
Chapman, Ken, Fast Integer Multipliers, pp. 28-31, Mar. 1993.
Raju, Murigavel, Digital FIR Filter Design Using the MSP430F16x, Texas Instruments Application Report SLAA228-Nov. 2004, pp. 1-5.
Luu Pho M.
Parker Stephen B.
Toshiba America Research Inc.
Watchstone P&D, pllc
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