Multiplex communications – Channel assignment techniques – Details of circuit or interface for connecting user to the...
Reexamination Certificate
1998-05-28
2001-03-13
Marcelo, Melvin (Department: 2733)
Multiplex communications
Channel assignment techniques
Details of circuit or interface for connecting user to the...
C370S522000
Reexamination Certificate
active
06201817
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
This invention relates to the field of data processing in a telecommunications system, and more particularly to a system providing an interface between a serial communications link and a processor that is parallel in nature, such as a modem's central processing unit.
B. Description of Related Art and Advantages of the Invention
One piece of equipment often used in telecommunications systems is a UART, or Universal Asynchronous Receiver Transmitter. The UART is a device which interfaces a serial communications link to a microprocessor. When receiving data, the UART converts the serial link data (i.e., bits) into parallel data (i.e., bytes, words, etc.), which is then transferred to the microprocessor. When transmitting data, the UART converts parallel data from the processor into serial data.
UARTs are used in a variety of different types of telecommunications systems, including modems. In this example, the serial communication link may be an RS-232 serial cable connected to a data terminal equipment (DTE) and a data communications equipment (DCE), and the processor is a central processing unit (CPU) for the modem, such as a digital signal processor (DSP).
The efficiency overhead time spent by the DSP to service the UART's transmit(TX)/receive(RX) requests of the interface between the UART and the processor is critical for the overall performance of the system. Originally, the UART only had a storage capacity of one or two characters as received from the serial link, or transmitted by the CPU. When a character was received, the UART stored it in a temporary register (buffer). The UART either informed the processor that a character was read by issuing an interrupt signal to the processor, or the processor constantly polled (i.e., checked a data available status bit) the UART. Likewise, a single character buffer was found at the transmit (TX) side. This approach worked well until serial communication rates and processor workloads increased. The single character buffer was no longer sufficient. In particular, the “overhead” time spent by the CPU to store/retrieve characters from the UART of processor time per character was greater than the time to send the actual data on the serial link.
Consequently, a second prior art method was devised to reduce the average UART overhead. This method introduced an N-character deep first-in, first-out (FIFO) buffer in the UART. The processor was no longer interrupted on a character by character basis, but rather was interrupted every time the FIFO buffer collected N-characters. This method reduced average overhead more than the first method, but still required the processor to perform the task of moving the data from the UART into its own local memory, as well as requiring the UART to contain an embedded fixed depth local FIFO storage unit for the data to be TX'd/RX'd by the UART. With the advent of even higher communication rates and faster CPUs, this second method has also proven to be also inefficient.
Secondly, there is a need to detect special characters embedded within the data stream. Prior art methods provided for this detection through software means only. That is to say, the software controlling the UART must spend additional time/processing power to parse the data stream to determine if special characters are present.
This invention provides for a more efficient detection via a discrete hardware processing unit found within the UART. Characters can be specified through programmable registers found within the UART to provide additional flexibility in character choices.
The present invention provides a method and system for coupling the UART to the processor in a manner in which the processor is no longer involved in the data transfer from the UART to the processor, therefore it substantially reduces overhead on the processor. In addition, the invention no longer requires a fixed depth FIFO buffer arrangement embedded in the UART. As such, the present invention provides a much more efficient arrangement for transferring data between a serial communications link and a processor, allowing the entire system to operate at significantly faster rates than that obtained with known prior art methods. Further, a receive channel is provided in which control characters indicative of special control conditions are detected in a discrete hardware processing unit, not by the system processor. This further off-loads a substantial computational burden from the processor, enabling much higher data transfer rates between the UART and the processor.
SUMMARY OF THE INVENTION
In one aspect of the invention, a system provides an interface between a serial communications link and a processor. The system includes a transmit register and a receive register, the transmit register and receive register respectively transmitting and receiving data to and from the serial communications link. The transmit and receive registers can either be of the form of a serial shift register (as in the case of a UART), or in the form of a parallel register in which data bits are grouped into blocks (i.e, bytes, words) and these list block groups locked in parallel directly by a remote host system (as in the case of a null UART).
A system memory coupled to the transmit and receive registers and to the processor is also provided. The system memory includes a receive buffer providing temporary data storage and a transmit buffer. A receive register command processor, coupled to the receive register, is also provided for detecting the presence of a control character or characters in the incoming data stream associated with communication control conditions and identifying where in the data stream such control character or characters occurred.
A control state machine is also provided that is coupled to the system memory and the receive command processor. The control state machine is responsive to the receive register command processor to coordinate the transfer of blocks of data in the incoming data stream from the receive register to the receive buffer in the system memory.
The control state machine further comprising a means for monitoring the status of the receive buffer, such as whether the receive buffer is full or contains a full frame of data from the serial communications link. The control state machine issues a first interrupt signal to the processor to initiate retrieval of data in the receive buffer and processing of the data when the receive buffer is filled to a predetermined amount (such as containing a frame of data). The control state machine further issues a second signal to the processor or otherwise indicates to the processor the location in the receive buffer where the control character or characters associated with said communication control condition are located.
In the above system, the efficiency of transfer of data from the serial communication link and the processor may be improved. In particular, the processor is not involved in the data transfers: this is taken over by the receive command processor and the control state machine. Additionally, there is no temporary FIFO buffer required at the receive register, since a single system memory is provided which directly receives the data from the receive register. Further, the overhead of the processor is reduced as compared to prior art methods.
In another aspect of the invention, the control state machine further comprises a receive write pointer identifying a location in the receive buffer and the control state machine transfers a character from the receive register to a location in the receive buffer identified by the receive write pointer. The control state machine increments the receive write pointer such that a subsequent character from the receive register is stored in a subsequent memory location in the receive buffer. In this manner, the control state machine can monitor the fullness of the receive buffer and initiate an interrupt to the processing unit when the receive buffer has a full frame of data in it.
In a modem embodiment o
3Com Corporation
Marcelo Melvin
McDonnell & Boehnen Hulbert & Berghoff
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