Memory bank management and arbitration in multiprocessor compute

Details Memory bank management and arbitration in multiprocessor compute Memory bank management and arbitration in multiprocessor compute

1992-04-16

1995-05-02

Gossage, Glenn

Boots, shoes, and leggings

395325, 395400, 395725, 3642281, 3642283, 364230, 36424291, 36424292, 364243, 3642464, 364DIG1, G06F 1316, G06F 1314

Patent

active

054127882

ABSTRACT:
A memory management and arbitration technique that reduces system bus contention by eliminating memory bank conflicts employs a restrictive, distributive memory-arbitration scheme, and an improved address decoder for decoding addresses of software reconfigurable memory. In the memory-arbitration scheme, each commander node desiring access to a particular memory bank first determines whether that memory bank is "available" before initiating access to that memory bank, with the determination being made before requesting control of the system bus. A memory bank is "available" if it was not accessed during a predetermined number (e.g., two) of the immediately previously-occurring arbitrations for the system bus. The address decoder includes a mapping register that stores information concerning the addresses assigned to, and the structure of, the memory module. The address decoder also has an address/range decoder section, an interleaved decoder section, and a bank decoder section. The address/range and interleave decoder sections determine the memory module containing the address being decoded. This can be combined with the output of the bank decoder section to identify the particular memory bank on the system bus that contains the address.

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