Memory bank address calculation with reduced instruction executi

Details Memory bank address calculation with reduced instruction executi Memory bank address calculation with reduced instruction executi

1991-03-28

1992-08-25

Shaw, Gareth D.

Boots, shoes, and leggings

364DIG1, 3642511, 3642543, 3642554, 364787, 364788, 36523003, 3652385, G06F 932

Patent

active

051426366

ABSTRACT:
A microcomputer in which a higher address must be corrected according to a carry or borrow signal generated during address computation for memory reference based on each addressing mode. The microcomputer is provided with a databank register for holding the higher address and a temporary register for storing a value obtained by incrementing or decrementing by one digit the contents of the data bank register so that the higher order address may be corrected with neither increase in the number of instruction executing cycles nor loss of the memory area continuity.

REFERENCES:
patent: 3993891 (1976-11-01), Beck et al.
patent: 4573137 (1986-02-01), Ohhashi
An Intro to Digital & Analog IC Applications by S. Mitra 1980, pp. 111-115.
Intel, The 8080/8085 Microprocessor Book, pp. 22-23, p. 8, 1980.

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