Memory bandwidth optimization

Details Memory bandwidth optimization Memory bandwidth optimization

1994-12-19

1997-03-11

Tung, Kee M.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395427, 395840, 395853, 395872, 395806, 345185, 345201, G06F 1200

Patent

active

056110413

ABSTRACT:
A memory controller, particularly for use in a video controller, is provided which reduces the effect of page misses during memory access. A video port FIFO is provided for buffering data from a video port to a display memory. A CRT FIFO is provided for buffering data from a display memory to a display. If, during a video port FIFO cycle, a page miss is encountered, the video port FIFO cycle is terminated and processing passes to a CRT FIFO CYCLE. If a page miss is encountered during a CRT FIFO cycle, the subsequent video port FIFO cycle will shortened by a number of memory cycles to compensate for the additional memory cycles required by the page miss. Additional data accumulated in the video port FIFO may be transferred to the display memory during a retrace interval. In this manner, memory bandwidth is optimized by removing a non-aligned page miss as the worst case of memory bandwidth utilization.

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