Static information storage and retrieval – Interconnection arrangements
Patent
1997-12-17
1998-12-08
Nelms, David
Static information storage and retrieval
Interconnection arrangements
365 51, G11C 506
Patent
active
058479864
ABSTRACT:
The spacing of the bit lines and/or the master bit lines (MBLs) of a memory array is skewed to decrease the charging current required to precharge the bit-lines and or the master bit lines. In one embodiment of the invention, an integrated circuit (IC) includes an array of memory cells arranged in rows and columns, with a pair of bit lines (BLTi and BLCi) per column of memory cells with BLTi carrying the cell data and BLCi its complement. The bit lines are disposed within a first level of the IC and run generally parallel to each other wherein there is a certain capacitance, CINT, between each two paired bit lines (BLTi and BLCi) and a capacitance, CEXT, between the bit lines of adjacent columns. The bit lines are coupled to selected MBLs with the MBLs being paired so that one MBL of a pair (MBLT) carries bit line data and the other MBL of a pair (MBLC) carries the complement of that bit line data. The MBLs are formed on a second level of the IC and run generally parallel to each other wherein there is a capacitance (MCINT) between the two paired master bit lines and a capacitance (MCEXT) between the master bit lines of a pair and the adjacent master bit lines. The spacing between the bit lines is skewed in order to decrease CINT relative to CEXT, and/or the spacing between the MBLs is skewed in order to decrease MCINT relative to MCEXT.
REFERENCES:
patent: 4975874 (1990-12-01), Childers et al.
patent: 5214600 (1993-05-01), Otto et al.
Braden Stanton C.
Nelms David
Siemens Aktiengesellschaft
Tran Andrew Q.
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