Memory array with partitioned bit lines

Details Memory array with partitioned bit lines Memory array with partitioned bit lines

1986-06-02

1989-01-31

Popek, Joseph A.

Static information storage and retrieval

Read only systems

Semiconductive

G11C 1700

Patent

active

048021210

ABSTRACT:
A memory array having two separate sets of parallel bit lines, and a word line intersecting the sets of bit lines. The memory cells are floating-gate MOS transistors having gates coupled to associated ones of the word lines and source-to-drain paths connected between alternating ones of the sets of bit lines and ground lines.

REFERENCES:
patent: 4342099 (1982-07-01), Kuo
patent: 4460981 (1984-07-01), Van Buskirk et al.

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