Memory array on more than one die

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S191000, C365S051000

Reexamination Certificate

active

08059441

ABSTRACT:
For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

REFERENCES:
patent: 7692946 (2010-04-01), Taufique et al.
patent: 2004/0256638 (2004-12-01), Perego et al.
patent: 2005/0127490 (2005-06-01), Black et al.
patent: 2005/0236703 (2005-10-01), Kazi et al.
patent: 2007/0055917 (2007-03-01), Kashiwaya
patent: 2007/0220207 (2007-09-01), Black et al.
patent: 2007/0275539 (2007-11-01), Rashid et al.
patent: 2008/0017971 (2008-01-01), Hollis
patent: 2008/0054493 (2008-03-01), Leddige et al.
patent: 2008/0150088 (2008-06-01), Reed et al.
patent: 2008/0152356 (2008-06-01), Somasekhar et al.
patent: 2008/0155196 (2008-06-01), Black et al.
patent: 2009/0138688 (2009-05-01), Black et al.
Black, Bryan, et al., “3D Processing Technology and its Impact on iA32 Microprocessors”, IEEE International Conference on Computer Design, pp. 316-318, 2004.
Black, Bryan, et al., “Die Stacking (3D) Microarchitecture”, IEEE ACM International Symposium on Microarchitecture, pp. 469-479, Dec. 2006.
Healy, Michael, et al., “Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, No. 1, pp. 38-52, Jan. 2007.
Healy, Michael, et al., “Microarchitectural Floorplanning Under Performance and Thermal Tradeoff”, Proceedings of Design, Automation and Test in Europe, pp. 1288-1293; Mar. 6-10, 2006.
Loh, Gabriel H., et al., “Processor Design in 3D Die-Stacking Technologies”, IEEE Micro, vol. 27, No. 3, pp. 31-48, May-Jun. 2007.
Puttaswamy, Kiran, et al., “Dynamic Instruction Schedulers in a 3-Dimensional Integration Technology”, Great Lakes Symposium on VLSI, pp. 153-158, Apr. 30-May 2, 2006.
Puttaswamy, Kiran, et al., “Implementing Caches in a 3D Technology for High Performance Processors”, IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 525-532, Oct. 2-5, 2005.
Puttaswamy, Kiran, et al., “Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology”, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 6 pages, Mar. 2-3, 2006.
Puttaswamy, Kiran, et al., “Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors”, ACM IEEE Design Automation Conference, pp. 622-625, Jun. 4-8, 2007.
Puttaswamy, Kiran, et al., “The Impact of 3-Dimensional Integration on the Design of Arithmetic Units”, IEEE International Symposium on Circuits and Systems, 4 pages, May 2006.
Puttaswamy, Kiran, et al., 'Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor', Great Lakes Symposium on VLSI, pp. 19-24, Apr. 30-May 2, 2006.
Puttaswamy, Kiran, et al., “Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors”, International Symposium on High-Performance Computer Architecture, pp. 193-204, Feb. 10-14, 2007.
Reed, Paul, et al., “Design Aspects of a Microprocessor Data Cache using 3D Die Interconnect Technology”, IEEE International Conference on Integrated Circuit Design and Technology, pp. 15-18, May 9-11, 2005.
Tsai, Yuh-Fang, et al., “Three-Dimensional Cache Design Exploration Using 3DCacti”, IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 519-524, Oct. 2-5, 2005.
Xie, Yuan, et al., “Design Space Exploration for 3D Architectures”, ACM Journal on Emerging Technologies in Computing Systems, vol. 2, No. 2, pp. 65-103, Apr. 2006.
Anonymous, “Method for Effectively Using the Through-Silicon Via-Interconnect Area for Clock Distribution in a 3-D Multistrata IC”, IP.com Publication No. IPCOM000125119D, pages, May 19, 2005.

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