Memory array of integrated circuits capable of replacing faulty

Details Memory array of integrated circuits capable of replacing faulty Memory array of integrated circuits capable of replacing faulty

1991-12-31

1995-04-11

Atkinson, Charles E.

Excavating

371 81, G06F 1100

Patent

active

054065658

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

This invention relates to a data storage system which comprises an array of integrated circuits or semiconductor chips, each such chip including a memory consisting of an array of memory locations some of which may be faulty.
Memory chips suffer from a small number of faults which can arise during manufacture or can develop subsequently. Systems have been devised which can tolerate such faulty chips. The commonest form of fault tolerance in use is the incorporation of spare rows and columns of bits into each memory chip. After manufacture the defective row or column is identified by chip testing, and the spare/s programmed to replace the defective element. The programming is permanent, using e.g. laser cutting or electrical fuse blowing. This has proved to be a successful technique and is in use today by all memory manufacturers, see the review paper "Redundancy--the new device technology for circuits of the 80's", R. J. Smith, International Electron Devices Meeting, December 1982.
The so-called redundancy approach does suffer from limitations especially in the early part of a memory product manufacturing life cycle. The manufacturer has to predict the numbers and type of faulty elements, expected as a result of a specific manufacturing process, in order to design the appropriate number of spare rows and columns. The manufacturer's choice of spares is constrained by limits imposed by chip area and performance. Furthermore the programming technique may restrict the efficiency of element replacement. The programming is permanent, hence there is no provision for faults developing after some period of operational use.
An alternative approach is described in GB 2 184 268. Instead of trying to manufacture perfect storage devices by repairing imperfect chips in the factory (redundancy), it was proposed that imperfect devices be salvaged and only their good bits used. The technique suffers from one main drawback. During data transfer, large blank gaps will periodically appear. Whilst for a local computer these gaps could be identified and input or output suspended, a more remote system would have difficulty in stopping and starting. These gaps lead to a greatly reduced data transfer rate. A further disadvantage is a reduction in storage capacity.


SUMMARY OF THE INVENTION

In accordance with this invention, there is provided a fault tolerant data storage system which comprises an array of integrated circuits, each integrated circuit including a memory consisting of an array of memory locations some of which may be faulty, the system having means for addressing a plurality of integrated circuits in a row simultaneously for writing or reading data via parallel data lines, and means for identifying faulty locations and for connecting the data line for a faulty integrated circuit to a good location in a spare integrated circuit, the logical addresses for the integrated circuits being skewed differently for each other as compared with their physical addresses.
A typical memory chip comprises a two dimensional storage array of n columns along the horizontal axis and m rows along the vertical axis. A typical manufacturing fault will affect one or more columns and/or rows.
In the embodiments of this invention to be described herein, columns (or clusters of individual bit faults) are recovered by switching from faulty columns to good columns (spares) on-the-fly. This so called `dynamic sparing` is effective because modern memory devices have large numbers of columns (typically greater than 512). The spare columns are provided by an extra chip added to each row of the storage array.
During data transfer it is the column location that is addressed most frequently hence dynamic column sparing (DCS) has to operate autonomously at high speed. Since rows represent convenient data blocks a faulty row is spared before any transfer begins and used for the period of the transfer.
Row recovery is similar to DCS described above, and is known as Pre-emptive Row Sparing (PRS). PRS uses a spare row of chips

REFERENCES:
patent: 3735368 (1973-05-01), Beausoleil
patent: 4556975 (1985-12-01), Smith et al.
patent: 4584681 (1986-04-01), Singh et al.
patent: 4639897 (1987-01-01), Wacyk
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 4849938 (1989-07-01), Furutani et al.
patent: 5195057 (1993-03-01), Kasa et al.
Sy-Yen Kuo et al., Efficient Spare Allocation for Reconfigurable Arrays, Feb. 1987, pp. 24-30.

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