Memory array datapath architecture

Details Memory array datapath architecture Memory array datapath architecture

1999-01-25

2000-12-05

Hoang, Huan

Static information storage and retrieval

Interconnection arrangements

365 51, 36523003, 36523002, G11C 506

Patent

active

061575607

ABSTRACT:
A datapath structure (for use in conjunction with at least one memory array) that includes N local data lines, N global data lines, M global I/O lines, and a datapath. Each memory array is partitioned into a number of segments, and each segment is associated with one or more bit lines. Each segment is further associated with at least one local data line. Each local data line couples to the bit lines associated with that particular local data line. The N global data lines operatively couple to the N local data lines. The datapath interconnects the N global data lines to the M global I/O lines in accordance with a set of control signals. The datapath includes M local I/O lines, M multiplexer circuits, and M interface circuits. The M interface circuits interconnect the M global I/O lines and the M local I/O lines. Each of the M multiplexer circuits interconnects the M local I/O lines to N/M of the N global data lines. In a specific implementation, M is eight and N is sixty-four.

REFERENCES:
patent: 5940329 (1999-08-01), Seitsinger et al.
patent: 5949697 (1999-07-01), Lee
patent: 5959918 (1999-09-01), Arimoto
patent: 5995404 (1999-11-01), Nakaumura et al.

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