Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2008-04-08
2008-04-08
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S104000, C365S185030
Reexamination Certificate
active
07355876
ABSTRACT:
A high-speed nonvolatile memory array has two-bit memory cells, each connected to a mutually adjacent pair of sub-bit lines. The sub-bit lines are connected to a common power supply line through switching elements controlled in a cyclic sequence by 2m signal lines, where m is an integer greater than one. The memory array circuit also has main bit lines, each connected to a group of m consecutive sub-bit lines through switching elements controlled in a cyclic sequence by m signal lines. Data are read through two mutually adjacent main bit lines from two memory cells selected so that the sub-bit lines connecting the two main bit lines to the two memory cells are located between the sub-bit lines connecting the two memory cells to the common power line, an arrangement that reduces parasitic capacitance.
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Auduong Gene N.
OKI Electric Industry Co., Ltd.
Rabin & Berdo P.C.
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