Memory array architecture and method for dynamic cell plate sens

Details Memory array architecture and method for dynamic cell plate sens Memory array architecture and method for dynamic cell plate sens

1998-09-24

1999-07-20

Nelms, David

Static information storage and retrieval

Interconnection arrangements

365239, 36523009, 365191, G11C 506

Patent

active

059264101

ABSTRACT:
A memory array architecture is described which uses active digit lines at array edges. To maximize array area using active digit lines, a memory array architecture is employed where interior rows of memory cells intersect X columns of memory cells. Rows located along the edge of the array, however, intersect less than X columns of memory cells. Two rows of memory cells located along the edge of the array must be accessed together to form a complete row of X columns.

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