Memory array and method of operating a memory

Details Memory array and method of operating a memory Memory array and method of operating a memory

2011-08-23

2011-08-23

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S185180

Reexamination Certificate

active

08004899

ABSTRACT:
A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. A method of operating the memory array is also shown, including, in reading a selected memory cell, applying voltages to the gate, the drain and the source thereof respectively from a word line, a first global bit line and a neighboring second global bit line, and turning on a select transistor coupled to a third global bit line separate from the first and the second ones by at least one other global bit line.

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