Memory array

Details Memory array Memory array

1976-03-22

1977-08-23

Canney, Vincent P.

Communications: electrical

Digital comparator systems

G11C 1100

Patent

active

040443418

ABSTRACT:
A memory array includes row conductors which have to be charged to a first level prior to each read-out cycle. During a read-out cycle the row conductors may or may not be discharged to a second level depending on whether a "1" or a "0" is stored at selected bit locations. The memory array also includes "dummy" row conductors which are discharged to the second level each time the contents of the array are read out. Means are provided for charging the row conductors including the "dummy" row conductors to the first level prior to each read-out, for sensing the charge level on the "dummy" row conductors, and for terminating the charging cycle when the charge level on the "dummy" row conductors reaches the first level.

REFERENCES:
patent: 3735368 (1973-05-01), Beausoleil

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