Memory arrangement with selectable memory sectors

Details Memory arrangement with selectable memory sectors Memory arrangement with selectable memory sectors

2002-05-31

2003-12-16

Mai, Son L. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S185130

Reexamination Certificate

active

06665211

ABSTRACT:

The present invention relates to a memory arrangement having a plurality of memory cells grouped into memory sectors, the memory cells being arranged in particular matricially, i.e. in rows and columns, and sector switches being used for selecting/activating the individual memory sectors.
Non-volatile flash memories, which may be configured in the form of an external chip or such that they are integrated together with a corresponding logic system, are following the trend towards very large-scale integration just like other memory modules or, for example, logic modules as well. This entails smaller structure widths, with ever-larger memory capacities furthermore being required, in particular so that newer and more modern applications can be run properly. Another challenge due to the respective applications is the increasing need for read performance of the corresponding memory. This is all the more problematic since the read current of the individual memory cells also decreases as the structure widths are reduced. To solve this problem, the memory sectors, of which the respective memory is made up, are therefore to be reduced to such an extent that the respectively required reading speed can be achieved/guaranteed. In order to obtain an economically viable solution under these constraints, the so-called sector overhead, i.e. the ratio of the required drive circuits to the pure memory-cell array, must be as small as possible.
Sector switches are used for selecting/activating the individual memory sectors in conventional memory arrangements, and these sector switches have to date been produced area-intensively in the form of a corresponding logic system and/or corresponding high-voltage transistors. In conventional memory modules, the additional area requirement of the sector switches is, for example, about 20%.
It is therefore an object of the present invention to propose a memory arrangement having a plurality of memory cells grouped into memory sectors, with the possibility of minimising the previously described sector overhead, i.e. the additional area requirement due to the sector switches.
This object is achieved according to the invention by a memory arrangement having the features of claim
1
. The dependent claims define respectively preferred and advantageous embodiments of the present invention.
According to the invention, memory cells are used as sector switches in order to solve the aforementioned problem. In order to avoid any effect of high voltages on the threshold voltage of the memory cells configured as sector switches, the “floating gate” of the memory cells may optionally be short-circuited to the “control gate” of the memory cells. This is possible without additional outlay on technology or processing. The sector switches then function as pure MOS transistors, for example as pure NMOS transistors.
The individual memory cells are, in particular, arranged in the form of a memory matrix in rows and columns, for example with the memory cells of one column respectively forming a memory sector, or a memory block. In such a matricial memory arrangement, the drain and source terminals of the individual memory cells may in each case be interconnected via local bit lines and local source lines, respectively. The memory cells which are used as sector switches are then in each case arranged between the local bit line and a global bit line, or the local source line and a global source line, respectively. For an efficient configuration of the memory cells which are used as sector switches, the voltage path needed for programming and erasing is preferably separated from the voltage path needed for reading, the voltage path needed for programming and erasing being a so-called MV (“medium-voltage”) path and the read path being an LV (“slow-voltage”) path. The MV path is in this case routed via the global bit line to the drain terminal of the memory cell, whereas the control of the memory cell during reading takes place via the source terminal. In this case, en the grounds of performance enhancement, the sector switch present on the global source line may be boosted, for example to 6 V, and the selection of the respective memory sector may be carried out using LV transistors.
The present invention is preferably used to produce non-volatile flash memories. Nevertheless, the present invention is of course not restricted to this preferred application field, but can be applied in general to all types of memory in which memory cells are subdivided in the form of memory sectors, or memory blocks, and selection/activation of the individual memory sectors takes place via corresponding sector switches or sector switching means.


REFERENCES:
patent: 5623443 (1997-04-01), Kazerounian et al.
patent: 5646886 (1997-07-01), Brahmbhatt
patent: 6072722 (2000-06-01), Hirano

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