Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2006-02-21
2009-11-03
Dinh, Son (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S189020, C365S230020
Reexamination Certificate
active
07613023
ABSTRACT:
When recording uncompressed video and/or audio data using a digital video recorder, there is the need for a robust memory arrangement based on non-volatile, integrated circuits which is able to be fitted directly on the video camera without a long external cable connection and which is also able to be used for shots under difficult conditions, particularly action shots. The inventive memory arrangement involves the use of a number of non-volatile memory chips which are connected together with a favorable level of circuit complexity. To be able to cope with the high data rate for the incoming video and/or audio data, a plurality of parallel supply buses are provided. Each supply bus has an associated number of memory chips. In this case, the memory word length of the memory chips is greater than the bus width of a data/address bus. A supply bus with high-quality multiplexing has a respective associated number of demultiplexer/driver circuits which match the bus width of the supply bus to the memory word length of the memory chips. There are respectively as many downstream memory chips per demultiplexer/driver circuit as prescribed by a value X, the value X being limited by the memory technology used, namely by the maximum number of circuits which can be connected, also called the “fan-out” value. The memory chips used are preferably NAND Flash EPROM memory chips.
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Search Report Dated May 30, 2006.
Drexler Michael
Kochale Axel
Wittenburg Jens Peter
Dinh Son
Navon Jeffrey M.
Nguyen Nam
Shedd Robert D.
Thomson Licensing
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