Memory arrangement for processing data, and method

Details Memory arrangement for processing data, and method Memory arrangement for processing data, and method

2006-04-04

2006-04-04

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189120, C365S191000

Reexamination Certificate

active

07023760

ABSTRACT:
The invention relates to a memory arrangement for processing data and to a method for operating this memory arrangement. The inventive method involves a control signal being transferred together with the data on, with a change in the control signal activating the DLL circuit and synchronizing it to a clock. In this case, the DLL circuit stipulates a sampling time for the data. In line with the invention, after a predetermined length of time within which no data have been read from the memory, the memory is accessed artificially in order to generate a change in the control signal for the DLL circuit.

REFERENCES:
patent: 6094380 (2000-07-01), Kim
patent: 6414891 (2002-07-01), Kuge et al.
patent: 6608743 (2003-08-01), Suzuki
patent: 2001 118 385 (2001-04-01), None
Tran, “Synthesizable DDR SDRAM Controller”, Xilinx: XAPP200 Application Note (V2.4), Jul. 18, 2002.

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