Memory arrangement

Details Memory arrangement Memory arrangement

2005-09-30

2010-08-03

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Powering

C365S230030

Reexamination Certificate

active

07768862

ABSTRACT:
A memory arrangement including a memory array, which has at least one memory block with a power supply device which can be activated, an address decoder, which is coupled to the at least one memory block in order to control access to the at least one memory block, and an activation device for selectively activating the power supply device of memory blocks. The address decoder is set up to interact with the activation device in such a manner that, when a memory block is accessed for the first time, the power supply device of the memory block is activated and remains activated after the access operation has ended.

REFERENCES:
patent: 6125073 (2000-09-01), Le et al.
patent: 6195306 (2001-02-01), Horiguchi et al.
patent: 6792536 (2004-09-01), Teppler
patent: 2004/0085846 (2004-05-01), Yokozeki et al.
patent: 0871178 (1998-10-01), None

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