Memory architecture with segmented writing lines

Details Memory architecture with segmented writing lines Memory architecture with segmented writing lines

2006-11-21

2006-11-21

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000

Reexamination Certificate

active

07139212

ABSTRACT:
A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

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