Memory architecture with multilevel hierarchy

Details Memory architecture with multilevel hierarchy Memory architecture with multilevel hierarchy

1998-09-16

2000-10-31

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 711117, G11C 800

Patent

active

061412872

ABSTRACT:
The memory is made up of memory cells disposed in a memory architecture with multilevel hierarchy. Many external connection ports are provided. Such memories are generally called multiport memories. The novel multiport memory architecture with multilevel hierarchy typically has one-port memory cells in the lowermost hierarchical level. The memory blocks in the respectively higher hierarchical levels are each made up of memory blocks from the next lower hierarchical level. By the defined multiport memory architecture with multilevel hierarchy, the expenditure for surface area on the chip can advantageously be reduced. The memory blocks in the hierarchical levels can, depending on requirements, be disposed in a memory block matrix in a switching network, a banking technique arrangement, and so forth. Depending on the desired application, the greatest possible freedom of design is provided. The multiport memory architecture also has a circuit for handling access contentions. The novel memory architecture can be applied to all memory technologies as well as to logic technologies.

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"A Single Chip Multiprocessor for Multimedia: The MVP" (Guttag et al.), IEEE 1992, pp. 53-65.

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