Memory architecture with graphics generator including a divide b

Details Memory architecture with graphics generator including a divide b Memory architecture with graphics generator including a divide b

1991-10-07

1993-12-07

Chin, Tommy P.

Computer graphics processing and selective visual display system

Display driving control circuitry

Physically integral with display elements

345 28, G09G 102

Patent

active

052686817

ABSTRACT:
A video display system includes a frame buffer comprising five sets of one or more VRAMs. An address generator for generating address locations in the frame buffer generates chip select, row select and column select address signals. Because the frame buffer comprises five sets of VRAMs, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memory capacity in the frame buffer.

REFERENCES:
patent: 4967392 (1990-10-01), Werner et al.
patent: 4991110 (1991-02-01), Hannah
patent: 5038297 (1991-08-01), Hannah

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