Memory architecture with enhanced over-erase tolerant...

Details Memory architecture with enhanced over-erase tolerant... Memory architecture with enhanced over-erase tolerant...

2007-02-20

2007-02-20

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185300, C365S185330

Reexamination Certificate

active

11178965

ABSTRACT:
The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.

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