Boots – shoes – and leggings
Patent
1995-01-11
1996-02-20
Chan, Eddie P.
Boots, shoes, and leggings
364DIG1, 36424341, 3642543, 3642384, G06F 1208
Patent
active
054936667
ABSTRACT:
A memory architecture including a memory cache which uses a single level of write buffering in combination with page mode writes to attain zero wait state operation for most memory accesses by a microprocessor. By the use of such a memory architecture, the speed advantages of more expensive buffering schemes, such as FIFO buffering, are obtained using less complex designs. The memory architecture utilizes same page detection logic and latching circuitry and takes advantage of a feature built into industry standard dynamic RAMs, namely page mode writes, to perform writes to memory which allow the processor to be freed before the write is completed for the most frequently occurring type of write operations.
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Apple Computer Inc.
Chan Eddie P.
Nguyen Hiep T.
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