Memory architecture having multiple partial wordline drivers...

Details Memory architecture having multiple partial wordline drivers... Memory architecture having multiple partial wordline drivers...

2011-08-30

2011-08-30

Dinh, Son T (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S230020, C365S203000

Reexamination Certificate

active

08009506

ABSTRACT:
Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines.

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