Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-04-19
2001-06-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185260, C365S189060
Reexamination Certificate
active
06243294
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application relates to
1. U.S. patent application Ser. No. 09/552,280 entitled “REDUNDANCY SCHEME TO IMPROVE PROGRAMMING YIELD FOR NON-VOLATILE MEMORY USING GATE BREAKDOWN STRUCTURE IN STANDARD SUB 0.25 MICRON CMOS PROCESS” commonly owned and filed concurrently with the present application.
2. U.S. patent application Ser. No. 09/552,571 entitled “NON-VOLATILE MEMORY ARRAY USING GATE BREAKDOWN STRUCTURES” commonly owned and filed concurrently with the present application.
3. U.S. patent application Ser. No. 09/524,971 entitled “INTELLECTUAL PROPERTY PROTECTION IN A PROGRAMMABLE LOGIC DEVICE” commonly owned and filed Mar. 4, 200.
These related applications are incorporated herein by reference.
TECHNICAL FIELD
This invention relates to integrated circuits, particularly programmable logic devices or field programmable gate arrays (FPGAs). More particularly, this invention relates to memory architectures for use in non-volatile memory arrays that are incorporated into FPGAs.
BACKGROUND OF THE INVENTION
Many integrated circuits now in use are fabricated in what is called CMOS (complimentary metal oxide semiconductor) technology, which forms both PMOS and NMOS transistors on a silicon substrate. One of the main objectives of integrated circuit technology is to minimize transistor size. Transistors are typically described in terms of their minimum feature dimension.
Current technology provides a minimum feature size of 0.35 micron or less. The minimum feature size, which is also referred to as a “line width”, refers to the minimum width of a transistor feature such as the gate width, or the separation between source and drain diffusion regions. Typically, 0.35 micron technology is used to form CMOS transistors having a gate oxide thickness of 70 Å (angstroms). A 0.18 micron technology is used to form CMOS transistors having a gate oxide thickness of around 35-40 Å. A 0.15 micron technology is used to form CMOS transistors having a gate oxide thickness of around 25-30 Å. The gate “oxide”, is typically an oxide dielectric layer that is interposed between the conducting gate electrode, which is typically a polycrystalline silicon structure formed overlying the principal surface of a substrate in which the integrated circuit if formed, and the underlying substrate which typically is the channel portion of the transistor extending between the source and the drain regions. Transistors formed using the 0.35 micron technology typically operate at a voltage of 3.3 volts. Transistors formed using the 0.18 micron technology typically operate at a voltage of 1.8 volts. Greater voltages are likely to destroy the transistor by rupturing the gate oxide. Sub 0.35 micron processes provide for two different transistor families having different gate oxide thicknesses. A first transistor family has a thin gate oxide and a second transistor family has a thick gate oxide.
In the field of data storage, there are two main types of storage elements. The first type of storage element is a volatile storage element such as typically used in DRAM (dynamic random access memory) or SRAM (static random access memory) in which the information stored in a particular storage element is lost when power is removed from the circuit.
The second type of storage element is a non-volatile storage element in which the information stored in the storage element is preserved even if power is removed from the circuit. Typically, the types of elements used to provide non-volatile storage are substantially different from those used in ordinary logic circuitry or in volatile storage, thereby requiring different fabrication techniques.
It has heretofore not been possible to include non-volatile storage on an integrated circuit chip formed exclusively using standard CMOS processes.
SUMMARY OF THE INVENTION
Memory architectures for use in non-volatile memory arrays and methods of programming memory cells are described. In the described embodiments, the cell structure can be fabricated using standard CMOS processes, e.g., sub 0.35 micron or sub 0.25 micron processes. Alternatively, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS process. Particular embodiments may be implemented in a FPGA.
In particular embodiments, the cell structures are fabricated using a standard 0.18 micron CMOS process. In these embodiments, memory cells are fabricated using storage structures, including transistors, having different gate breakdown characteristics (e.g., as impacted by the thickness of their gate dielectric layers). The memory cells are programmed by taking advantage of the different gate breakdown characteristics.
In one embodiment, a FPGA includes an array of memory cells and a word line coupled to a row of memory cells in the array. A second signal line is coupled to the row of memory cells and extends in parallel with the word line. The second signal line applies a zero voltage to the memory cells when programming a memory cell in the row of memory cells. A positive voltage is applied to the second signal line when programming a memory cell outside the row of memory cells.
According to another implementation, each memory cell includes a storage transistor and an access transistor coupled to the storage transistor.
In another embodiment, each memory cell is programmed by breaking the gate oxide of a storage transistor in the memory cell.
In a further embodiment, a memory cell is programmed by selecting a word line and a bit line associated with the memory cell being programmed. A zero voltage is applied to a third control signal line coupled to the memory cell and extending in parallel with the word line. A programming voltage is applied to the selected bit line to program the memory cell.
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Hart Michael J.
Rao Kameswara K.
Voogel Martin L.
Le Thong
Nelms David
Xilinx , Inc.
Young Edel M.
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