Memory architecture for high speed network devices

Details Memory architecture for high speed network devices Memory architecture for high speed network devices

2006-06-12

2011-12-13

Ahmed, Salman (Department: 2476)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S413000

Reexamination Certificate

active

08077610

ABSTRACT:
An embodiment of the present invention reduces certain memory bandwidth requirements when sending a multicast message from a network device such as a router, bridge or switch. Separate output buffers are provided for different groups of egress ports, and incoming messages are written to some or all of the output buffers. A processing determination is made as to which egress ports will forward the message. Buffers associated with non-forwarding ports are released and the message is queued at the forwarding egress ports. When the message is forwarded, data is read from the output buffers associated with the forwarding egress ports.

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