Boots – shoes – and leggings
Patent
1983-06-29
1986-01-07
Zache, Raulfe B.
Boots, shoes, and leggings
371 16, G06F 1300
Patent
active
045637369
ABSTRACT:
A single computer board data processing system includes a multiport memory system which is accessible by I/O controllers through a system bus I/O memory port or directly by the system's central processing unit (CPU) via a CPU memory port. The logic and control circuits of the memory ports and CPU are included within the computer main board while memory modules/pacs are contained on one or more memory daughter boards which plug into memory input/output connectors contained on the main board. The port address and data paths connect in common to the memory connectors for transmitting and receiving memory addresses and data between the memory modules and the CPU and I/O ports. At least one register connects between the CPU and to common address path. When the CPU is placed in a diagnostic mode of operation, this register together with existing data registers are conditioned to store signals representative of the address and data being transmitted to the memory modules enabling the CPU to diagnose whether the main board or portions thereof has failed without requiring any testing of the memory modules.
REFERENCES:
patent: 4371952 (1983-02-01), Schuck
Boudreau Daniel A.
Salas Edward R.
Zelley Richard C.
Driscoll Faith F.
Honeywell Information Systems Inc.
Solakian John S.
Zache Raulfe B.
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