Memory architecture for burst mode access

Details Memory architecture for burst mode access Memory architecture for burst mode access

1996-11-08

1998-07-28

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

365236, 395405, 395855, 395873, G11C 700, G11C 800

Patent

active

057870470

ABSTRACT:
The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable. A particular embodiment for generating an aligned sequential burst address sequence is described.

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