Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2002-02-19
2003-06-10
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S230060
Reexamination Certificate
active
06577521
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuit memory architectures and more particularly to addressing of decoders contained therein.
BACKGROUND OF THE INVENTION
Integrated circuit memories that are used for electronic data storage include dynamic random access memories (DRAMs), static random access memories (SRAMs), electrically erasable and programmable read only memories (EEPROMs), synchronous random access memories or other types of memories that include a matrix of selectively addressable memory cells.
For example,
FIG. 1
is a floorplan block diagram that illustrates the architecture of a conventional DRAM
100
, which typically includes a matrixed arrangement of multiple memory cell arrays
105
, each of which is understood to contain a matrixed arrangement of memory cells. The interstitial separations between the memory cell arrays
105
carry support circuits for addressing the memory cells in the memory cell arrays
105
, such as for performing reading and writing operations. The interstitial separations include longitudinal streets
110
and latitudinal streets
115
.
Longitudinal streets
110
typically include column decoder and sense amplifier circuits, which together are adjacent to or interposed between ones of memory cell arrays
105
. The column decoder and sense amplifier circuits are used for reading data from and writing data to selected digit lines, which are in the memory cell arrays
105
and are coupled to memory cells therein. Latitudinal streets
115
typically include row decoders that are adjacent to or interposed between ones of memory cell arrays
105
. The row decoder circuits are used for selectively activating word lines in a memory cell array
105
for accessing memory cells therein.
The column decoder and sense amplifier circuits in the longitudinal streets
110
and the row decoder circuits in the latitudinal streets
115
are sometimes referred to collectively as “pitch cell” circuits, because such circuits are laid out on the same pitch (spacing between adjacent ones) of the digit lines and word lines to which they are respectively coupled. The interstitial separations between memory cell arrays
105
occupy a considerable portion of the integrated circuit DRAM. In order to improve storage density, for reducing the component size of integrated circuit DRAM
100
or for increasing the data storage capability of integrated circuit DRAM
100
, the magnitude of the interstitial separations between memory cell arrays
105
should be decreased, such as by electrical circuit design or physical layout design techniques. For example, it is known in the art to provide an output driver in a row decoder that is interposed between two memory cell arrays
105
, where an output node of the output driver provides an output signal to a word line in each of the memory cell arrays
105
between which the row decoder is interposed. This reduces the size of the row decoder and the magnitude of the interstitial separations between memory cell arrays.
However, even if such design techniques are successful, there is a need in the art to provide, in a spatially efficient manner, control signals (e.g., addressing signals) to the row decoders in the latitudinal streets
115
and to the column decoders in the longitudinal streets
110
. Thus, in order to fully realize the gains in storage density arising from reducing the magnitude of the interstitial separations between memory cell arrays
105
, there is a need in the art to accommodate such magnitude reductions when providing signals to the pitch cells carried within the interstitial separations.
SUMMARY OF THE INVENTION
The present invention allows better utilization of the gains in storage density realized by reducing the magnitude of the interstitial separations between memory cell arrays in an integrated circuit memory. According to one aspect of the invention, such magnitude reductions are accommodated when providing signals to the pitch cells carried within the interstitial separations. In one embodiment, the invention provides an integrated circuit memory having a plurality of memory cell arrays arranged in a grid pattern. Adjacent ones of the memory cell arrays are laterally separated, thereby defining longitudinal streets. Adjacent ones of the memory arrays are vertically separated, thereby defining latitudinal streets. Gap regions are defined by intersections of the longitudinal and latitudinal streets. First and second decoders are located in the latitudinal streets and separated by the gap region. A decoder control circuit is located in the gap region and coupled to provide an output signal to the first and second decoders.
In another embodiment, the invention provides an integrated circuit memory having a plurality of memory cell arrays arranged in a grid pattern. Adjacent ones of the memory cell arrays are laterally separated, thereby defining longitudinal streets. Adjacent ones of the memory arrays are vertically separated, thereby defining latitudinal streets. A gap region is defined by an intersection of the longitudinal and latitudinal streets. A pair of row decoders is provided. The pair of row decoders is located in a latitudinal street. A first row decoder in the pair has X/2 inputs and is located on a first side of the gap region. A second row decoder in the pair has X/2 inputs and is located on an opposite side of the gap region. Together, the first and second row decoders have X inputs. A decoder control circuit is located in the gap region. The decoder control circuit provides X/2 output signals (e.g., shared pairwise) to the X inputs of the first and second row decoders.
In another embodiment, the invention provides an integrated circuit memory having a plurality of memory cell arrays. The memory cell arrays are arranged in a matrix with longitudinal and latitudinal streets bounding the memory cell arrays. A plurality of row decoders are placed in (and define a magnitude of) the latitudinal streets. Each row decoder is coupled to at least one of the memory cell arrays by a plurality of word lines. A plurality of sense amplifiers is placed in the longitudinal streets. Each sense amplifier is coupled to at least one of the memory cell arrays by at least one digit line pair. A plurality of column decoders is placed in the longitudinal streets and, together with the sense amplifiers, define a magnitude thereof. Each column decoder is coupled to at least one of the memory cell arrays by a plurality of digit lines. A plurality of decoder control circuits are included. Each decoder control circuit is placed in an intersection of one of the longitudinal streets and one of the latitudinal streets. Each decoder control circuit carries a plurality of drivers. Ones of the plurality of drivers are coupled to more than one row decoder for providing an address signal to the more than one row decoder.
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Le Vu A.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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