Static information storage and retrieval – Format or disposition of elements
Patent
1999-02-18
2000-03-14
Phan, Trong
Static information storage and retrieval
Format or disposition of elements
36523006, G11C 502
Patent
active
060381590
ABSTRACT:
A memory architecture includes a matrixed arrangement of memory cell arrays having interstitial separations bounding each memory cell array. The interstitial separations between memory cell arrays include longitudinal streets, carrying row decoders, and latitudinal streets, carrying column decoders that include sense amplifiers. Decoder control circuits are disposed in the intersections of the longitudinal and latitudinal streets. Each decoder control circuit includes drivers for providing addressing or other signals to pairs of adjacent row or column decoders. Each driver provides a signal to more than one decoder, such as to each of the row or column decoders between which the decoder control circuit is interposed. The decoder control circuit requires fewer drivers, which can be staggered or laterally offset to better accommodate magnitude reductions of the interstitial separations between memory cell arrays, thereby increasing storage density.
REFERENCES:
patent: 4748591 (1988-05-01), Itoh et al.
patent: 5400283 (1995-03-01), Raad
patent: 5526318 (1996-06-01), Slemmer et al.
patent: 5574698 (1996-11-01), Raad
patent: 5586080 (1996-12-01), Raad et al.
patent: 5706244 (1998-01-01), Shimizu
patent: 5717629 (1998-02-01), Yin
patent: 5892703 (1999-04-01), Raad
Le Thong
Micro)n Technology, Inc.
Phan Trong
LandOfFree
Memory architecture and decoder addressing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory architecture and decoder addressing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory architecture and decoder addressing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-175689