Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2006-05-18
2009-10-20
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S163000
Reexamination Certificate
active
07606055
ABSTRACT:
An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The other of the channel terminals are effectively tied together via reference lines. The word lines (i.e., gates) of the two access transistors are also tied together. The result in a preferred embodiment is a cell having two access transistors wired and accessed in parallel. With such a configuration, the widths of the access transistors can be made one-half the width of more-traditional one-access-transistor designs, saving layout space in that (first) dimension. Moreover, because the word lines of adjacent cells will be deselected, the improved design does not require cell-to-cell isolation (e.g., trench isolation) in the other (second) dimension. The result, when applied to a phase change memory, comprises about a 37% reduction in layout area from previous cell designs.
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Micro)n Technology, Inc.
Nguyen Van-Thu
Wong Cabello Lutsch Rutherford & Brucculeri LLP
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