Memory architecture

Details Memory architecture Memory architecture

2007-06-26

2007-06-26

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S189080, C257S758000, C257S211000

Reexamination Certificate

active

10879158

ABSTRACT:
A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

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