Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1990-07-10
1993-05-18
Bowler, Alyssa H.
Static information storage and retrieval
Addressing
Plural blocks or banks
395425, 395400, 365 51, 365 63, G11C 800, G06F 1200
Patent
active
052126668
ABSTRACT:
A memory apparatus has a W(1+J/N) (words).times.D (bits) configuration employing (N+J) semiconductor memory units having (N+J) W (words).times.B (bits) semiconductor memory elements wherein N=D/B=2.sup.d-b and J is a positive integer wherein J<N; W=2.sup.w and w is a positive integer; and B=2.sup.b where b is zero or a positive integer satisfying b<d. For example, five 256K.times.4 1M DRAMs are employed so that four out of five DRAMs always correspond to access from a microprocessor. Furthermore, a 640-Kbyte memory address space is equally divided into five 128-Kbyte memory address areas and the correspondence between the 128-Kbyte memory address areas and four out of the five DRAMs is regularly determined in turn, thereby constituting a 640-Kbyte memory apparatus (320 Kwords.times.16 bits) employing only 1M DRAMs. More particularly, a memory capacity can be set in relatively small units, i.e., in units of W.multidot.J/N words.times.D bits by employing only semiconductor memory units of a single type.
REFERENCES:
patent: 4592022 (1986-05-01), Shimohigashi et al.
patent: 4633443 (1986-12-01), Childers
patent: 4893280 (1990-01-01), Gelsomini et al.
Bowler Alyssa H.
Carothers, Jr. W. Douglas
Seiko Epson Corporation
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