Memory apparatus

Details Memory apparatus Memory apparatus

1995-10-31

1997-06-10

Zarabian, Amir

Static information storage and retrieval

Hardware for storage elements

36518909, 365195, 3652301, G11C 502

Patent

active

056383169

ABSTRACT:
The present invention relates to a memory apparatus to be able to do write protection and aims to protect data in a specified area in a memory device not to be easily rewritten.
When address signals A11 to A0 outputted from a microprocessor are written in the area 300 to 3FF, a CS signal from an address decoder for memory selection to a memory device is "enable" and it is possible to read from and write in the memory device. In the case in which the address signals are written in the area 3F0 to 3FF, the address decoder for write protection becomes "enable" and an output of an AND circuit is selected by a selector and is supplied to the memory device as a WE signal. If a write control signal is "enable", the WE signal outputted from the microprocessor is not masked by the AND circuit and it is possible to write in the memory device.

REFERENCES:
patent: 5130946 (1992-07-01), Watanabe
patent: 5402385 (1995-03-01), Ozeki et al.

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