Memory apparatus

Details Memory apparatus Memory apparatus

1991-10-18

1994-08-30

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sequential

365236, 365219, 36518912, 36518907, 365221, G11C 700

Patent

active

053434390

ABSTRACT:
A memory apparatus includes a memory cell array for storing a data, a shift register for receiving an input serial data to be stored in the memory cell array and supplying an output serial data to be read from the memory cell array, and a transfer gate for transferring a data in parallel between the shift register and the memory cell array. In the shift register, the input serial data is shifted to an output side thereof until the first bit reaches to the final step thereof. Then, the input serial data is transferred to be stored in the memory cell array by the transfer gate. Thus, when the stored data is read therefrom, no invalid bit is supplied even at the beginning time even if the shift register is longer than the input serial data.

REFERENCES:
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4987559 (1991-01-01), Miyauchi et al.
patent: 4989181 (1991-01-01), Harada
patent: 5084839 (1992-01-01), Young
patent: 5195055 (1993-03-01), Mizuoka et al.

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