Memory and method operating the memory

Details Memory and method operating the memory Memory and method operating the memory

2009-04-08

2011-12-13

Nguyen, Dang (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S053000

Reexamination Certificate

active

08077522

ABSTRACT:
A memory comprises a memory array, a sense unit, and a biasing and shielding circuit. The biasing and shielding circuit is coupled to the memory array and the sense unit, wherein the biasing and shielding circuit comprises a first transistor, a second transistor, and a capacitor. The first transistor has a gate coupled to a biasing voltage and a first terminal coupled to the sense unit. The second transistor has a gate coupled to the biasing voltage and a first terminal coupled to a first potential. The capacitor is coupled to the sense unit and the first transistor.

REFERENCES:
patent: 5018105 (1991-05-01), Miyanishi
patent: 7130236 (2006-10-01), Rajwani et al.
patent: 7433230 (2008-10-01), Kono et al.
patent: 2002/0075731 (2002-06-01), Amano
patent: 2003/0026145 (2003-02-01), Lee

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