Memory and method of writing data

Details Memory and method of writing data Memory and method of writing data

2007-01-11

2009-10-06

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Addressing

Sequential

C365S185180

Reexamination Certificate

active

07599247

ABSTRACT:
Semiconductor memory devices10are each furnished with a memory array100having an EEPROM array101and a mask ROM array102. Identifying information for identifying each semiconductor memory device10is stored at the beginning three addresses of the EEPROM array101. 8-bit data relating to ink level is stored at the ninth address to sixteenth address of the EEPROM array101. The seventeenth address to the twenty-fourth address of the EEPROM array101is provided with a usage history information storage area for storing 8-bit usage history information that is rewriteable under certain conditions.

REFERENCES:
patent: 7059700 (2006-06-01), Aihara
patent: 7499372 (2009-03-01), Asauchi
patent: 2002/0060703 (2002-05-01), Tsukada
patent: 2004/0183845 (2004-09-01), Aihara
patent: 2008/0144382 (2008-06-01), Asauchi
patent: 05-282879 (1993-10-01), None
patent: 2001-187455 (2001-07-01), None

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