Static information storage and retrieval – Addressing – Plural blocks or banks
Reissue Patent
2000-04-26
2001-10-16
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060, C365S230080
Reissue Patent
active
RE037409
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of computer memories. More specifically, the present invention relates to sub-word line access in computer memories.
BACKGROUND OF THE INVENTION
Memory cells are typically physically and logically oriented in rows and columns, and share word lines and bit lines, respectively. In a dynamic random access memory, for example, a memory cell consists of a transistor and a capacitor connected to a bit tine and a word line. The word line selects a memory cell. The bit line is what connects the memory cell to the sense amplifier to transfer data.
This is illustrated in the simplified diagram of FIG.
1
a. Referring to
FIG. 1a
, a word line metal
110
, is coupled to word line gate polysilicon
115
which runs in parallel with word line metal
110
. Metal-polysilicon straps
120
are periodically added to reduce resistance. When the word line metal
110
is activated, word line gate polysilicon
115
is activated and enables the sense amplifiers
125
to sense or restore data to/from the coupled memory cells (not shown). The operations performed by sense amplifiers
125
are controlled by control signals
127
,
129
.
FIG. 1b
illustrates a dual word line example. In this example, word line metal
110
is selectively connected to one of two word line gate polysilicon
117
,
119
through AND gates
130
,
135
. Typically the AND gates are placed at intervals along the word lines and
110
, gate polysilicon
117
,
119
corresponding to locations of word line straps. Select signals
140
,
145
, which are complementary signals, are input to the AND gates
130
,
135
to select the word line gate polysilicon to couple to the word line metal.
Some manufactures have encountered performance problems utilizing longer word line lengths. This is due to increased capacitance and resistance. To minimize longer word line lengths effects, the word line polysilicon is broken up into a plurality of segments. When the word line metal is activated, all of the segments are activated, effectively activating the entire word line polysilicon composed of the segments.
All of these circuits require that the entire word line gate polysilicon associated with a particular row of memory cells be raised, even if only a small portion of the row of memory cells required access. In addition, the entire column of sense amplifiers is activated to perform the memory operation. For example, if a read operation is performed with respect to a subset of a row of memory cells, the entire word line gate polysilicon associated with a particular row of memory cells and the entire column of sense amplifiers are activated to transfer the data of the entire row to the sense amplifiers. It follows that a restore operation on the entire row is subsequently required.
One disadvantage associated with the this approach is that a significant amount of power is required to bring an entire row of information into the sense amplifiers. Another disadvantage associated with this approach is that the sense amplifiers can only store data from one row of memory cells at a time. Therefore, data that was placed there before will need to be flushed even if that particular data is required immediately afterwards.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a memory in which power efficient memory accesses can be performed.
It is an object of the present invention to provide for sub-word memory accesses.
It is another object of the invention to provide for a memory in which sets of sense amplifiers corresponding to different sub-words of rows of memory can communicate data to different rows of the memory.
A memory design and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group. The sub-word lines are further coupled to the memory cells in the row of the corresponding sub-group. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power.
In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Barth Richard M.
Lai Lawrence
Richardson Wayne S.
Stark Donald C.
Fears Terrell W.
Rambus Inc.
Shemwell Charles E.
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