Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1996-12-20
1998-05-05
Fears, Terrell W.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523006, B11C 1300
Patent
active
057485542
ABSTRACT:
A memory and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group and is coupled to the memory cells in the row of the corresponding sub-group. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.
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Barth Richard M.
Lai Lawrence
Richardson Wayne S.
Stark Donald C.
Fears Terrell W.
Rambus Inc.
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