Memory and driving method therefor

Details Memory and driving method therefor Memory and driving method therefor

2007-11-13

2007-11-13

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S104000

Reexamination Certificate

active

11391990

ABSTRACT:
A memory and a driving method therefor is provided. A j-th bank select MOS transistor is coupled to a j-th bit line and controlled by a bank select line. A j-th BD region is coupled to the j-th bank select MOS transistor. Gate(i, j) of memory cell M (i, j) is coupled to the i-th word line, the first source/drain(i, j) of memory cell M (i, j) is coupled to the j-th BD region, and the second source/drain(i, j) of memory cell M (i, j) is coupled to the first source/drain(i, j+1). In order to compensate the voltage drop resulting from the resistance of the j-th bit line and the j-th BD region, at least one of the voltage applied to the i-th word line and the voltage applied to the j-th bit line is adjusted according to the position of the bank which the memory cell M (i, j) belongs to.

REFERENCES:
patent: 6278649 (2001-08-01), Lee et al.
patent: 6430079 (2002-08-01), Shiau

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