Memory and driving method of the same

Details Memory and driving method of the same Memory and driving method of the same

2007-01-02

2007-01-02

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S094000

Reexamination Certificate

active

10890173

ABSTRACT:
A memory having a bit line, a word line crossing the bit line, a memory cell electrically connected to the bit line and to the word line, a column decoder and a selector including a clocked inverter having a plurality of transistors electrically connected in series between a first power source and a second power source is provided. An input node of the clocked inverter is connected to the bit line, an output node of the clocked inverter is electrically connected to a data line, the plurality of transistors comprise a P-type transistor and a N-type transistor, a gate electrode of the P-type transistor and a gate electrode of the N-type transistor are electrically connected to the column decoder, and a sense amplifier is not interposed between the bit line and the input node of the clocked inverter.

REFERENCES:
patent: 5297029 (1994-03-01), Nakai et al.
patent: 6741487 (2004-05-01), Yokozeki
patent: 2001/0030323 (2001-10-01), Ikeda
patent: 05-166381 (1993-07-01), None
patent: 06-020484 (1994-01-01), None
patent: 07-065594 (1995-03-01), None

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