Memory and control unit

Details Memory and control unit Memory and control unit

2009-03-02

2010-10-26

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189050, C365S230080

Reexamination Certificate

active

07821868

ABSTRACT:
A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an operation rewriting the second address or the amount of the first data and an operation continuously holding the first address and the second address or the amount of the first data.

REFERENCES:
patent: 4829484 (1989-05-01), Arimoto et al.
patent: 5267097 (1993-11-01), Ogino et al.
patent: 5881010 (1999-03-01), Artieri
patent: 5986914 (1999-11-01), McClure
patent: 6414894 (2002-07-01), Ooishi et al.
patent: 6646944 (2003-11-01), Shimano et al.
patent: 6868027 (2005-03-01), Kawaguchi
patent: 6898108 (2005-05-01), Kato et al.
patent: 6901479 (2005-05-01), Tomita
patent: 7055001 (2006-05-01), Miura
patent: 7245545 (2007-07-01), Miyamoto
patent: 7518944 (2009-04-01), Miyamoto
patent: 2003/0028745 (2003-02-01), Hosoi
patent: 2003/0086312 (2003-05-01), Kang
patent: 2005/0141258 (2005-06-01), Kang et al.
patent: 2005/0207203 (2005-09-01), Kang
patent: 2005/0213419 (2005-09-01), Miyamoto
patent: 2008/0181022 (2008-07-01), Fujisawa et al.
patent: 63-247997 (1988-10-01), None
patent: 02-231621 (1990-09-01), None
patent: 04-358243 (1992-12-01), None
patent: 05-046359 (1993-02-01), None
patent: 70-73682 (1995-03-01), None
patent: 30-63716 (1999-08-01), None
patent: 11-272444 (1999-10-01), None
patent: 2000-105991 (2000-04-01), None
patent: 2001-229674 (2001-08-01), None
patent: 2002-344905 (2002-11-01), None
patent: 2002-369124 (2002-12-01), None
patent: 2003-123470 (2003-04-01), None
patent: 2004-199842 (2004-07-01), None
patent: 2005078756 (2005-03-01), None
patent: 2005-115720 (2005-04-01), None
patent: 2006-092640 (2006-04-01), None
patent: 2003-123466 (2010-05-01), None
patent: 02/11138 (2002-02-01), None
Japanese Office Action, JP 2006-285959, Jan. 13, 2009, Japan.
Japanese Office Action, JP 2006-285959, May 13, 2008, Japan.
Notice of Allowability, U.S. Appl. No. 11/762,566, mailed on Oct. 31, 2008.
Office Action mailed Aug. 5, 2008 in U.S. Appl. No. 11/739,336.
Notice of Allowance mailed Jan. 22, 2009 in U.S. Appl. No. 11/739,336.
Office Action mailed Sep. 11, 2009 in U.S. Appl. No. 11/739,336.
Notice of Allowance mailed Jan. 27, 2010 in U.S. Appl. No. 11/739,336.
Notice of Allowance mailed Mar. 16, 2009 in U.S. Appl. No. 11/760,383.
Notice of Allowance mailed Aug. 12, 2008 in U.S. Appl. No. 11/762,566.
Office Action mailed Apr. 1, 2008 in Japanese Patent Application No. 2006-250483.
Office Action, mailed Jun. 6, 2010, for JP Patent Application 2007-109364, 6 pages.

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