Memory and control circuit for the memory

Details Memory and control circuit for the memory Memory and control circuit for the memory

1976-12-21

1978-10-24

Shaw, Gareth D.

Boots, shoes, and leggings

365238, G11C 906

Patent

active

041225317

ABSTRACT:
A memory and control circuit for the memory with a memory including a first memory plane area having a plurality of memory cells arranged in a matrix array and a plurality of second memory plane areas each having a plurality of nonvolatile memory cells arranged in a matrix array, the first memory plane area being arranged in a superposed relation to the second memory plane area and the memory cell in the first memory plane area being connected to the corresponding memory cell in the second memory plane area; first control lines connected to the second memory plane areas; a first control circuit for selectively driving the control lines to energize the memory cells in the corresponding second memory plane area; a second control line connected to the first memory plane area; and a second control circuit adapted to selectively energize the memory cells of the first memory plane area through the second control line to permit data transfer between the selected memory cell in the first memory plane area and that corresponding memory cell in the second memory area which is energized through the first control line.

REFERENCES:
patent: 3699535 (1972-10-01), Klein
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3916390 (1975-10-01), Chang et al.

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