Memory and buffer arrangement for digital computers

Details Memory and buffer arrangement for digital computers Memory and buffer arrangement for digital computers

1974-04-01

1976-02-10

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 1300

Patent

active

039380971

ABSTRACT:
Random access storage facilities for the CPU of a computer are cascaded in that a facility of relatively fast access speed holds a subset of information held in a facility of lower speed. Memory read requests are applied sequentially to these storage facilities, beginning always with the one of highest access speed, while requests satisfied by a lower speed facilities lead to storage of that information in all facilities of higher access speed. Write requests are made only to one facilities of lower speed, with algorthmic updating of the facility of lowest speed while the ones of higher speed are updated only on subsequent read requests for the same location. The several facilities which can be updated make storage space available on the basis of usages. The specific example explaining the invention has a conventional random access memory, a CPU associated cache and an buffer interposed between cache and memory with speed access ratio of 9:3:1, and cache and buffer sizes respectively leading to less then 50% cache access misses and less than 10% buffer misses, the average access time is better than half the access time of the memory alone.

REFERENCES:
patent: 3618040 (1971-11-01), Iwamoto et al.
Morenoff et al., "Application of Level Changing to Multilevel Storage Organization" Communications of ACM, Mar. 1967, pp. 149-154.
Opler, A., "Dynamic Flow of Programs and Data Through Hierarchical Storage" Information Processing, 1965, Vol. 1, pp. 273-276.

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