Memory and associated method including an operating mode for sim

Details Memory and associated method including an operating mode for sim Memory and associated method including an operating mode for sim

1991-12-23

1994-11-22

Gossage, Glenn

Boots, shoes, and leggings

364DIG1, 36523006, 3652385, G06F 1200, G11C 11413

Patent

active

053676556

ABSTRACT:
A memory (10) that has a shorter access time and higher reliability in a special mode of operation. In one form, the memory (10) has a special mode of operation in which multiple memory rows are simultaneously selected. As a consequence, multiple memory cells (44) are used to drive each bit line pair. Using multiple memory cells (44) to drive each bit line pair allows the bit lines to be driven to the proper logic state in a shorter time. This speeds up accesses to memory (10). Using multiple memory cells (44) to drive each bit line pair also improves the reliability of memory (10). Because multiple memory cells (44) are used to drive the same bit line pair, a failure of one memory cell (44) still leaves one or more functioning memory cells (44) to drive the correct logic state on the bit line pair. The memory may be incorporated in a cache controller of a data processing system in which only a part of the memory is being used. The extra unneeded memory cells may be used to help drive the bit lines to allow the cache controller to execute operations more quickly.

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McAdams et al., "A 1-Mbit CMOS Dynamic RAM With Design-For Test Functions", IEEE Journal of Solid State Circuits, Oct. 1986, vol. SC-21, No. 5, pp. 635-642.

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