Memory allocation for multiple processors

Details Memory allocation for multiple processors Memory allocation for multiple processors

1987-04-01

1989-05-02

Shaw, Gareth D.

Boots, shoes, and leggings

3642543, 3642532, 3642384, 3642455, G06F 1206

Patent

active

048274062

ABSTRACT:
A plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a hardware register to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory.

REFERENCES:
patent: 4173783 (1979-11-01), Couleur et al.
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4669043 (1987-05-01), Kaplinsky

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